The present invention relates generally to design automation, and relates more particularly to automatic test pattern generation (ATPG) for detecting process variation delay defects in integrated circuit (IC) chips.
When IC chips come off the manufacturing line, the chips are tested “at-speed” to ensure that they perform correctly (and to filter out chips that do not perform correctly). In particular, a set of paths is selected, and the set of paths is then tested for each chip in order to identify the chips in which one or more of the selected paths fail timing requirements. Selection of these paths is complicated by the presence of process variations. Because of these variations, different paths can be critical in different chips. That is, a path that is critical in one chip may not be critical in another chip, and vice versa. As such, selection of the paths that have a higher probability of being critical is typically a goal.
Once these paths are selected, they are sensitized by a test pattern generation tool. Unfortunately, many paths are not capable of being tested because they are either not sensitizable at all or not sensitizable within a relatively reasonable period of time. In fact, studies have shown that up to eighty-one percent of path delay faults in ISCAS-85 benchmark circuits cannot be sensitized. Thus, much time and computational resources may be wasted in the generation of paths that are later rejected because they cannot be sensitized. Moreover, the quality of the test is significantly reduced due to rejection of the paths that cannot be sensitized.